Field emission displays ("FEDs") are flat panel displays for use in computers, television sets, instrument displays, camcorder view finders and a variety of other applications. FEDs generally have a face plate with a substantially transparent anode covering an inner surface of a glass panel and a cathodoluminescent film covering the anode. FEDs also have a baseplate with an emitter substrate and an extraction grid. FIG. 1 illustrates a portion of a conventional FED baseplate 20 with an emitter substrate 30 that carries a plurality of emitters 32. The emitter substrate 30 also carries a dielectric layer 40 with a plurality of cavities 42 around the emitters, and the dielectric layer 40 supports a conductive extraction grid 50 with a plurality of holes 52 over the emitters 32. The cavities 42 and the holes 52 expose the emitters 32 to the face plate (not shown).
FIG. 2 is a top schematic view of the baseplate 20 that illustrates one technique for extracting electrons from selected emitters. The emitters 32 may be grouped into discrete emitter sets 33 configured in rows (e.g., R.sub.1 -R.sub.3) and columns (e.g., C.sub.1 -C.sub.2). A number of high-speed row interconnects 60 on the extraction grid 50 commonly connect a plurality of emitter sets 33 along row address lines, and a number of high-speed column interconnects 70 on the emitter substrate 30 commonly connect emitter sets 33 along column address lines. As best shown in FIG. 1, the row interconnects 60 are formed on top of the extraction grid 50 and the column interconnects 70 are formed on top of the emitter substrate 30 and beneath the extraction grid 50. It will be appreciated that the row and column assignments illustrated in FIGS. 1 and 2 are for illustrative purposes only, and that other row/column assignments may be implemented in field emission displays.
To operate a specific emitter set 33, drive circuitry (not shown) generates row and columns signals along the coordinates of the specific emitter set 33 to create a voltage differential between the extraction grid and the specific emitter set. Referring to FIG. 2, for example, a row signal along row R.sub.2 of the extraction grid 50 and a column signal along column C.sub.1 of the emitter substrate 30 activates the emitter set 33 at the intersection of row R.sub.2 and column C.sub.1. The voltage differential between the extraction grid 50 and the selected emitter set 33 produces a localized electric field that extracts electrons from the emitters 32 in the selected emitter set. The anode on the face plate then attracts the extracted electrons across a vacuum gap between the extraction grid and the cathodoluminescent layer. As the electrons strike the cathodoluminescent layer, light emits from the impact site and travels through the anode and the display screen. The emitted light from each area becomes all or part of a picture element.
One manufacturing concern with FEDs is that it can be difficult to fabricate high-speed interconnects for the address lines in the baseplate. To form the interconnect 70, for example, a conductive layer is deposited onto the top of the substrate 30 prior to forming the emitters 32. The conductive layer is then patterned and etched to form the interconnect 70. The emitters 32 are subsequently constructed by depositing an emitter material on the substrate 30, patterning the emitter material, and then etching the emitter material with processes known in the art. The difficulty in fabricating the high-speed interconnects 70 arises because etching the metal layer is a dirty process that may befoul the substrate with contaminants. Even when the substrate is thoroughly cleaned, some of the contaminants may remain on the substrate and impair the performance of the baseplate.
Another manufacturing concern with FEDs is that the interconnects increase the difficulty of fabricating the extraction grid over the emitter substrate. The conventional interconnect 70 shown in FIG. 1 increases the step height over which the dielectric layer 40 and grid 50 must conform during the fabrication. Large step heights in the grid generally increase the complexity of planarizing the grid conductor during formation of the self-aligned holes over the emitters. Additionally, large step heights may also increase the complexity of depositing the dielectric and conductive layers, particularly in low temperature processes that do not have good conformal coverage over steep topographies. To avoid problems and defects produced by the increased complexity in depositing and planarizing the dielectric and conductive layers, the processes are generally slowed down to ensure that cracks do not form at large steps and that the baseplate is planarized to the correct endpoint. Reduced processing speeds increase the cost and difficulty in producing field emission displays. Also, even when great care is exercised in forming the extraction grid, large step heights may cause defects that impair the performance of the baseplate. Conventional interconnects, therefore, limit the ability to economically and reproducibly fabricate large quantities of field emission displays.